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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
D D D D D D D D D D
128 x 1 Sensor-Element Organization 400 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required
(TOP VIEW)
1 SI HOLD 2 3 CLK GND 4 5 GND
Description
The TSL1401CS linear sensor array consists of a 128 x 1 array of photodiodes, associated charge amplifier circuitry, and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 m (H) by 55.5 m (W) with 63.5-m center-tocenter spacing and 8-m spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock.
AO 6 7 SO VDD 8
Functional Block Diagram
Pixel 1 Integrator Reset Pixel 2 Pixel 3 Pixel 128 Analog Bus Output Buffer Sample/ Output 6 AO 8 VDD
_ +
4, 5 GND
Switch Control Logic 2 Q1 Q2 Q3 Q128 Gain Trim 7 SO
Hold
CLK SI
3 1
128-Bit Shift Register
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Terminal Functions
TERMINAL NAME AO CLK GND HOLD SI SO VDD NO. 6 3 4, 5 2 1 7 8 Analog output Clock. The clock controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to the substrate. Hold signal. HOLD freezes the result of a 128 pixel scan. Serial input. SI defines the start of the data-out sequence. Serial output. SO provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. Supply voltage. Supply voltage for both analog and digital circuits. DESCRIPTION
Detailed Description
The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. The signal called Hold is normally connected to SI. Then, the rising edge of SI causes a HOLD condition. This causes all 128 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. Simultaneously, during the first 18 clock cycles, all pixel integrators are reset, and the next integration cycle begins on the 19th clock. On the 129th clock rising edge, the SI pulse is clocked out of the shift register and the analog output AO assumes a high impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel, and return the internal logic to a known state. A subsequent SI pulse may be presented as early as the 130th clock pulse, thereby initiating another pixel output cycle. AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout Vdrk Re Ee tint is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(J/cm2) is the incident irradiance in W/cm2 is integration time in seconds
A 0.1 F bypass capacitor should be connected between VDD and ground as close as possible to the device. The TSL1401CS is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding.
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Absolute Maximum Ratings
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . - 0.3 V to VDD + 0.3 V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 25 mA to 25 mA Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 100C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 100C Solder reflow temperature, case exposed for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, Clock frequency, fclock Sensor integration time, tint (see Note 1) Setup time, serial input, tsu(SI) Hold time, serial input, th(SI) (see Note 2) Operating free-air temperature, TA 3 0 2 0 400 5 0.016 20 0 -40 85 NOM 5 MAX 5.5 VDD VDD 0.8 1000 8000 100 UNIT V V V V nm kHz ms ns ns C
NOTES: 1. This time does not include the 18 clock cycles for setup, which would consume an additional 0.002 mS of device integrate and read time. 2. SI must go low before the rising edge of the next clock pulse.
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25C, p = 640 nm, tint = 5 ms, RL = 330 , Ee = 11 W/cm2 (unless otherwise noted) (see Note 3 and Note 4)
PARAMETER Vout Vdrk PRNU Analog output voltage (white, average over 128 pixels) Analog output voltage (dark, average over 128 pixels) Pixel response nonuniformity Nonlinearity of analog output voltage Output noise voltage Re Vsat SE DSNU IL IDD VIH VIL IIH IIL Ci Responsivity Analog output saturation voltage Saturation exposure Dark signal nonuniformity Image lag Supply current High-level input voltage Low-level input voltage High-level input current Low-level input current Input capacitance VI = VDD VI = 0 5 Ee = 0 See Note 5 See Note 6 See Note 7 See Note 8 VDD = 5 V, RL = 330 VDD = 3 V, RL = 330 VDD = 5 V, See Note 9 VDD = 3 V, See Note 9 All pixels, Ee = 0 See Note 11 VDD = 5 V, Ee = 0 VDD = 3 V, Ee = 0 2 0.8 1 1 See Note 10 25 4.5 2.5 TEST CONDITIONS MIN 1.6 0 TYP 2 0.1 4% 0.4% 1 35 4.8 2.8 136 78 0.02 0.5% 2.8 2.6 4.5 4.5 mA V V A A pF 0.05 V nJ/cm 2 V 44 MAX 2.4 0.2 10% FS mVrms V/ (J/cm 2) UNIT V V
NOTES: 3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 4. All measurements made with a 0.1 F capacitor connected between VDD and ground. 5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. Re(min) = [Vout(min) - Vdrk(max)] / (Ee x tint) 9. SE(min) = [Vsat(min) - Vdrk(min)] x Ee x tint) / [Vout(max) - Vdrk(min)] 10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100
Timing Requirements (see Figure 1 and Figure 2)
MIN tsu(SI) th(SI) tw tr, tf Setup time, serial input (see Note 12) Hold time, serial input (see Note 11 and Note 13) Pulse duration, clock high or low Input transition (rise and fall) time 20 0 50 0 500 NOM MAX UNIT ns ns ns ns
NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 13. SI must go low before the rising edge of the next clock pulse.
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 3 and 4)
PARAMETER ts Analog output settling time to 1% TEST CONDITIONS RL = 330 , CL = 10 pF MIN TYP 120 MAX UNIT ns
TYPICAL CHARACTERISTICS
CLK
SI
Internal Reset 18 Clock Cycles Integration Not Integrating Integrating
129 Clock Cycles AO Hi-Z
tw CLK tsu(SI) SI
AO
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Hi-Z
Figure 1. Timing Waveforms
1
2
128
129 2.5 V
5V 0V 5V 0V
50% th(SI)
ts
ts
Pixel 1
Pixel 128
Figure 2. Operational Waveforms
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
TYPICAL CHARACTERISTICS
SETTLING TIME vs. LOAD
600 VDD = 3 V Vout = 1 V 500 Settling Time to 1% -- ns Settling Time to 1% -- ns 470 pF 400 220 pF 300 500 470 pF 400 220 pF 300 600 VDD = 5 V Vout = 1 V
SETTLING TIME vs. LOAD
200 100 pF 100 10 pF 0
200 100 pF 100 10 pF
0
200 400 600 800 RL -- Load Resistance - W
1000
0
0
200 400 600 800 RL -- Load Resistance - W
1000
Figure 3
Figure 4
SUPPLY CURRENT vs FREE-AIR TEMPERATURE
4 VDD = 5 V Ee = 0 RL = 330 W IDD -- Supply Current -- mA 3
PHOTODIODE SPECTRAL RESPONSIVITY
1 TA = 25C
0.8 Relative Responsivity
0.6
2
0.4
0.2
1
0 300
0 400 500 600 700 800 900 - Wavelength - nm 1000 1100 0 10 20 30 40 60 50 TA - Free-Air Temperature - C 70
Figure 5
Figure 6
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
TYPICAL CHARACTERISTICS
WHITE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
2 VDD = 5 V tint = 0.5 ms to 15 ms Ee = Varies Vout -- Output Voltage -- V 1.5 Vout -- Output Voltage -- V 0.090 0.100 VDD = 5 V tint = 0.5 ms tint = 1 ms
DARK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
1
0.080 tint = 15 ms tint = 5 ms 0.070 tint = 2.5 ms
0.5
0 0 10 20 30 40 60 50 TA - Free-Air Temperature - C 70
0.060 0 10 20 30 40 60 50 TA - Free-Air Temperature - C 70
Figure 7
Figure 8
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
APPLICATION INFORMATION
A 0.1 F bypass capacitor should be connected between VDD and ground as close as possible to the device. The HOLD pin on the device is normally connected to the SI pin in single-die operation. In multi-die operation of n die, the HOLD pin is used to provide a continuous scan across the n die. See Figure 9 for an example of this wiring configuration. Note that there is a single AO signal when used in this mode. Alternately, the individual die may be scanned all at once by connecting the individual SI and HOLD lines and reading the AO signals in parallel. See Figure 10 for an example of this wiring configuration.
VDD
C1 0.1 mF
C2 0.1 mF
C3 0.1 mF AO
8 1 VDD SI TSL1401CS 2 3 HOLD CLK GND 5 GND CLK SI 4 5 SO 7 2 3 AO 6 1 SI
8 VDD AO TSL1401CS HOLD CLK GND 4 5 SO 7 2 3 6 1 SI
8 VDD AO TSL1401CS HOLD CLK GND 4 SO 7 6
Figure 9. Multi-Die Continuous Scan
VDD
C1 0.1 mF
C2 0.1 mF
C3 0.1 mF AO1 AO2
8 1 VDD SI TSL1401CS 2 3 HOLD CLK GND 5 GND CLK SI 4 5 SO 7 2 3 AO 6 1 SI
8 VDD AO TSL1401CS HOLD CLK GND 4 5 SO 7 2 3 6 1 SI
8 VDD AO TSL1401CS HOLD CLK GND 4 SO 7 6 AO3
Figure 10. Multi-Die Individual Scan
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
APPLICATION INFORMATION
TOP
BOTTOM
Figure 11. Device Pictorial
8 y 380 Diameter Mask
8 y 360 Diameter Metal Pad 170
1
2
3
4
5
6
7
8
8 y 110 Trace Width
7 y 1000
NOTES: A. All linear dimensions are in micrometers. B. This drawing is subject to change without notice.
Figure 12. Suggested PCB Layout
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MECHANICAL INFORMATION
The TSL1401CS is available in a solder bump linear array package, ready for surface mount manufacturing processes.
8870 + 25
TOP VIEW
1000 + 25
8120
A
SIDE VIEW
655 + 30
8
y 145 + 30
935 + 30
BOTTOM VIEW
4
y 170
4
y 415 + 30
Pin Pin Pin Pin Pin Pin Pin Pin
1 2 3 4 5 6 7 8
SI HOLD CLK GND GND AO SO VDD
430.4 + 25
NOTES: A. All linear dimensions are in micrometers. B. Unless otherwise noted, all dimensions are 10. C. This drawing is subject to change without notice.
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Pixel 1 Pixel 128 Alignment Marker (Pin 8)
B
7
y 1000
DETAIL A
128
DETAIL B
4 375 + 25 128
y 63.5
y8
y 55.5
4
y 265 + 25
625
127
y 63.5
Figure 13. Packaging Configuration
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MECHANICAL INFORMATION
0.300 + 0.200 1.24 + 0.100
SIDE VIEW
1.75 + 0.100 Pin 1
j 1.5 + 0.100 Typ 2 + 0.100
4 + 0.100 Typ 4 + 0.100
TOP VIEW
A 7.50 + 0.100 16
C L
+ 0.300 - 0.100
A R 0.58 B B
DETAIL A
DETAIL B
Ko 0.82 85 Max Bo 7.60 9.17
1.29 Ao 1.17 55 Max NOTES: A. B. C. D. E. F. All linear dimensions are in millimeters. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001. Each reel is 178 millimeters in diameter and contains 2800 parts. TAOS packaging tape and reel conform to the requirements of EIA Standard 481-B. This drawing is subject to change without notice.
Figure 14. TSL1401CS Carrier Tape
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
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MANUFACTURING INFORMATION
This product has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. The process, equipment, and materials used in these tests are detailed below.
Tooling Required
D Solder stencil (round aperture size 0.36 mm, stencil thickness of 152.4 m) D 20 x 20 frame for solder stencil
Process
1. Apply solder paste using stencil 2. Dispense adhesive dots 3. Place component 4. Reflow solder/cure 5. X-Ray verify Placement of the TSL1401CS device onto the gold immersion substrate is accomplished using a standard surface mount manufacturing process. First, using the stencil with 0.36 mm square aperture, print solder paste onto the substrate. Next, dispense two 0.25 mm to 0.4 mm diameter dots of adhesive in opposing corners of the TSL1401CS mounting area. Machine place the TSL1401CS from the JEDEC waffle carrier onto the substrate. A suggested pick-up tool is the Siemens Vacuum Pickup tool nozzle number 912. This nozzle has a rubber tip with a diameter of approximately 0.75 mm. The part is picked up from the center of the body. Reflow the solder and cure the adhesive using the solder profile shown in Figure 15.
250
200 Temperature -- 5C
150
100
50
0 0 50 100 150 200 250 Time - s 300 350 400 450 500
Figure 15. TSL1401CS Solder Profile It is important to use a substrate that has an immersion plating surface. This may be immersion gold, silver, or white tin. Hot air solder leveled substrates (HASL) are not coplanar and should not be used.
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS036A - AUGUST 2003
MANUFACTURING INFORMATION Qualified Equipment
D EKRA E5 -- Stencil Printer D ASYMTEC Century -- Dispensing system D SIEMENS F5 -- Placement system
- SIEMENS 912 -- Vacuum Pickup Tool Nozzle
D VITRONICS 820 -- Oven D PHOENIX -- Inspector X-Ray system
Qualified Materials
D OMG -- Microbond solder paste D Loctite 3621 -- Adhesive
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TSL1401CS 128 x 1 LINEAR SENSOR ARRAY WITH HOLD
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PRODUCTION DATA -- information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER'S RISK.
LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced Optoelectronic Solutions Incorporated.
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